Nice work. Hopefully, there might eventually be some Haiku tutorials on OS system tweaking - such as getting it working on RISC-V & ARM. Just simple stuff to get ppl up-&-running. Then there could be several ppl working on this kind of thing and making great progress.
1 Like
regarding the arm32 port: recently i tried to update some of the guides on haiku website,
e.g. here:
https://www.haiku-os.org/docs/develop/kernel/arch/arm/overview.html
any suggestion what other kind of tutorials would you find useful?
1 Like
Iāve continued working on getting this to boot on the StarFive VisionFive.
Iāve been able to get the haiku sources and build tools to cross compile the RISC-V builds and make some changes to the bootloader to help me verify some things. Iāve added in some explicit printf statements to track progress and can confirm that the bootloader is successfully finding and loading the kernel, but the lack of output seems to be related to the dprintf function not working correctly on this board. Iām still not sure if thereās an issue with the RISC-V implementation of this function and the VisionFive or if the lack of debug output is something else. Hopefully I can get debug output working soon.
14 Likes
Another RISC board from Pine64:
6 Likes
pricing ?? availability ???
1 Like
The Roma is available from Alibaba (opens in new tab) as a basic package for $1,499, which comes with a warranty of āmore thanā five years and free spare parts. Thereās also a $4,999 āpremiumā package that sees extras like headphones and a smartwatch added to the deal, along with the chance to have your name engraved on the laptopās casing.
1 Like
USD ? $1499 ??? not sure if serious
1 Like
What did you expect? Designing a new CPU isnāt cheap and for now this has very small production volumes (1100 untis will be made if I understand correctly). Weāll have to wait a bit for these to become more popular and grow, for now itās very early days for RISC-V systems and this canāt yet compete with mass produced x86 hardware.
3 Likes
RISC-V SBCs are already about to catch up with the Raspberry Pi. Give it a few years and I would expect there to be something similar to the Pinebook Pro but with a RISC-V CPU.
3 Likes
Unfortunately PineBook Pro is pretty slow too. This RISC laptop looks nice, would love to test it, but its far too expensive for me.
1 Like
I think RISC-V has potential to combat ARM in power, heat production, price and energy use as a result of being open for anyone to contribute to. ARM is too cheaply designed and produced while not really being as powerful as itās other RISC brothers (PowerPC needs to make a comeback).
1 Like
The RISC processors that perform best are the ones that embrace CISC characteristics. I still have a G4 Mac Mini running MorphOS and a Teron Mini derivitave running AmigaOS 4.1FE2 and I am content to leave PPC in the grave.
I have a Pinebook Pro and it is certainly weak but putting a smaller, faster operating system can make up for that performance lag in some instances. MorphOS runs nice and fast on my 1.5 GHz G4 system but even its new web browser doesnāt have a JIT compiler for its JavaScript engine. In most instances the cache characteristics of the operating system only make up for a little bit of the performance lags.
The number one predictor of performance on a cache enhanced CPU is code density. It improves the capabilities of the code cache. Thatās why CISC, not RISC, must make a comeback. I miss the 680x0 more than PPC.
1 Like
CISC never went away, complex instruction sets in my opinion have been limiting CPU design and innovation for years. If you want to read up on a phenomenal piece of RISC hardware, look up the Playstation 3ās Cell CPU co-developed by Sony and IBM
3 Likes
I think weāll just have to agree to disagree. RISC instruction sets are slower because of their bloat. Iām no fan of x86 though.
2 Likes
, no reason to argue, weāre all here because we love Haiku.
4 Likes
fixed width pipelines i suspect are the actual bottle neck. flexible width pipelines with assignable lanes are probably next gen. or mixed width pipelines, get rid of the concept of a core. dispatch unit selection of pipeline allocation from instruction stream, them allows dispatch to utilize all of the lanes like threads, i think CPUs already do something like this with cache and int units but iirc the pipelines are fixed width per core. would require significant os and compiler and language changes afaict
1 Like
Replied in CPU architecture thread.
1 Like
but its far too expensive for me.
will the situation improve with visionfive 2?
3 Likes
impressive specs on that board !!
1 Like