This continues a CPU architecture discussion from the RISC-V thread:
@SCollins
fixed width pipelines i suspect are the actual bottle neck. flexible width pipelines with assignable lanes are probably next gen. or mixed width pipelines, get rid of the concept of a core. dispatch unit selection of pipeline allocation from instruction stream, them allows dispatch to utilize all of the lanes like threads, i think CPUs already do something like this with cache and int units but iirc the pipelines are fixed width per core. would require significant os and compiler and language changes afaict
There’s an advanced RISC-V CPU core written in Chisel called BOOM on GitHub. Maybe that would be a useful starting point.
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I’m not a cpu designer, but i suspect things may head this way
Yeah. The design of BOOM has about a 7-stage pipeline and is 3-way superscalar. My suspicions are that if the macro-expansions of the instruction cracker were made deeper than 4 micro-ops using a higher density CISC instruction set, it could be made faster yet. Also, making it hyperthreaded could reduce the speculative nature of the micro-op queue. That would improve the resiliance to mispredicted branches and reduce the number of micro-ops needing to be cancelled during a misprediction.
I only have a two-year degree in electronic engineering technology besides my four-year degree in computer science but the fact that BOOM is an open-source core and is advanced as it is, I find fascinating! Hopefully the Chisel language makes these designs more attainable to hobbyists like myself, than what System Verilog and VHDL are.
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