NewOS kernel NextGeneration ? Haiku R2


#1

Hi,

I’am pass out with Haiku, for nevermind reasons. But I’am interests a some teorethical things like Genetic Algoritms. With information engineering, Googling, Wolfing etc. I shot in a few material with experymental land GA Scheduler and I’am wonder it is a time to make new kernel like genetic or hybrid neural network-genetics.
You take a question WHY ?
How to fallow abstract material this kernel is fully Parallel, error of calculations is 0,5-07 %. One fault i fund is a long “warm up” a population to make something.

so long peace out


#2

Firefly BSD has very good SMP. That is what they have gone for.

I’ve wondered also about future of PRISM computing. I’m wondering if Haiku could have new kernel for staged movement towards it as a major platform.

1 Gain big dev and user base. (perhaps by upgrading existing legacy systems)
2 Integrate Firefly SMP abilities
3 Transition over to RISC-V PRISM (Parallel Reduced Instruction Set Microprocessor) systems

Within that, complex computing of CAD or Machine Learning make sense to use the power of PRISM.

Is that the sort of thing you were thinking about?


#3

My thesis is completely experimental. At this moment, the development of microprocessors goes in the direction of parallelism. I have no information if such a kernel would be efficient, without the use of special optimization techniques. This kernel would be a completely new approach to OS communication and processor. Ordinarily, I would like to create a commercial project and a parallel community open source, which would build as a possibility new features of such a kernel. I realize that this is a laborious process. But it gives hope to Haiku and other operating systems for the same as not the code from other systems like BSD.

Cheers!


#4

Hi pvalue

Have you seen the GRVI Phallanx RISC-V architecture?
If I understand it correctly, then maximising efficiency of a PRISM chip involves choosing the right mix of accelerators. So for simple database it would just be throwing IO around really fast, but for complex stuff it would combine more pieces together. So you have basic RISC components, but additional “accelerators” throughout the chip with the right mix that you get good traffic flow.

But that is the hardware side. I don’t know how a kernel would work. So your idea is really interesting!

And yeah, the future is parallel. I think its PRISM in the home and business as mini mainframe with PDA workstations hooked up to the local PRISM based cloud.