What do you mean? You don’t need a GPU to get VSync synchronization. It was possible since the very first CGA and MDA cards on PC, and probably a bit before that on other machines. You do, however, need hardware decoding for these video formats if your CPU is not so fast.
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Alright, now I’m a little bit more interested in the VisionFive.
There is also the Nezha by Sipeed and RVBoards.
It is only $99 USD. However considering the lack of performance optimisations for RISC-V in Haiku and the low specs, I assume that it probably would not be a wise purchase at this point and time.
Those specs look a bit too low for me.
Maybe Haiku could boot with it in a few minutes,but as soon as I open a webpage in Falkon,it will fill up the whole RAM and crash.
1GB is something you can’t really use for a desktop computer anymore nowadays,2GB is already quite difficult and you have to think twice before opening a big program.
I use a pentium M laptop with 2GB with haiku and browse the web with it fine, maybe falkon just isn’t the best option to use there.
I didn’t say that it will instantly crash on 2GB,but on the 1GB that the Nezha SBC offers.
On 2GB you can still do some basic stuff,but if you want to use Falkon with 10 Tabs,KDevelop and Quaternion at the same time,it will also become difficult 
QT apps are not that memory efficient indeed, you can use native apps instead
If you show me a good native IDE and a native Matrix client,I’ll be happy to use it 
…but I feel this discussion goes too off-topic now…
The RISC-V Summit is December 6-8, 2021, so starting today: RISC-V Summit | Linux Foundation Events
Hopefully there will be some announcement of new hardware…
Interested can have an eye or two on the hash tag #RISCVSummit on Twitter today and the next following days…
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I may be dumb but is Sparc RISC based?
“SPARC was one of the most successful early commercial RISC systems” (Wikipedia)
Aight so it is RISC… would this build work on Sparc then? I’m getting a Sun machine here in a few weeks and I could totally help with testing
I highly doubt it, SPARC almost certainly has a very different instruction set. That said, PulkoMandy was working with getting Haiku on some Sun hardware within the recent past, I think.
Ooh, that’s awesome
RISC != RISC-V
RISC is a whole family of CPU architectures,and RISC-V is one of them.
Others are SPARC,PowerPC or ARM (Advanced RISC Machines).
They have something common in their design (I don’t know what exactly it is,maybe Wikipedia does),but they also have big differences between each other and are not compatible to each other.
A RISC-V port won’t help to run Haiku on SPARC,neither will the ARM port help with it.
There is a dedicated SPARC port of Haiku,but I don’t know if it actually works or if anyone actively maintains it: https://download.haiku-os.org/nightly-images/sparc/
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I’ll definitely test it once I get my Sun machine
Yepp, if you want and able to build development environment… that’s NOT a ‘boot and run’ version actually. 
It is even more complicated than that…
“RISC” is a geneal concept. It means “reduced instruction set computer”. It is not even a family, just a general idea of how to design a CPU. This was a debate in the 1980s and 1990s. Before that, all CPUs were simple because people had to manually place all transistors and they could not fit a lot of transistors in a CPU.
As technology improved, people expanded CPUs in two possible directions:
- CISC was about adding more and more instructions, all highly specialized. For example the CPU could have hardware to compute a logarithm, trigonometry functions, all kind of crazy things.
- RISC, on the other hand, was about keeping the instructions simple and not add a lot of them. Instead, the extra transistors would be used to add a lot of CPU registers, and try to make all the instructions execute as fast as possible.
SPARC and ARM were in the RISC family, but over time they added more instructions anyway. On the other side, the x86 family is a good example of a CISC design, but in the 64bit version they added a lot more registers too. It turns out there is so much transistors in CPUs now that you can have the best of both worlds.
On the RISC side, there is a series of CPUs initially designed for research purposes. They are named RISC-I, RISC-II, etc using roman numerals, and each generation is not compatible with the previous (the goal is to experiment with some features, see what works and what doesn’t, and then design a new architecture keeping the best things, removing the useless ones, and trying something else). RISC-V is the last of these. SPARC is initially based on one of the older generations, but with incompatible changes as well.
So, the SPARC and RISC-V architectures are completely different, even if they are somewhat historically related.
The Haiku SPARC port is indeed very early work and pretty much only the bootloader is working at the moment. So there is not a lot to test, yet. For this reason we also don’t provide ready-to-use disk images yet, so you’d have to set up a development environment and attempt to compile it yourself. And I have not even generated disk images for my own testing: currently I load the bootloader and root filesystem over the network.
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Ah, shame. There’s not much out there for Sparc so it’d be cool if someone could make an OS so that these old Sun machines can be given new life again
To add complexity to the argument, most cisc CPUs now are risc cpus beyond the decoders anyways. X86 is mostly a decoder front end
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