It seems compatible, but I have not tried yet except UART that is used for U-Boot commands and viewing Haiku syslog.
1 Like
Would the Starfive Linux drivers be of help for supporting the LAN port?
1 Like
Or U-Boot code: u-boot/dwc_eth_qos.c at JH7110_VisionFive2_devel · starfive-tech/u-boot · GitHub. It is simpler than Linux driver (~2000 lines of code) and can be used as reference for writing native Haiku driver.
9 Likes
Initializing second PCI domain:
+PciControllerPlda::InitDriver()
bus-range: 0 - 255
interrupt-map:
bus: 0, dev: 0, fn: 0, childIrq: 1, parentIrq: (5, 1)
bus: 0, dev: 0, fn: 0, childIrq: 2, parentIrq: (5, 2)
bus: 0, dev: 0, fn: 0, childIrq: 3, parentIrq: (5, 3)
bus: 0, dev: 0, fn: 0, childIrq: 4, parentIrq: (5, 4)
ranges:
MMIO32 (0x82000000): child: 30000000, parent: 30000000, len: 8000000
MMIO64 (0xc3000000): child: 900000000, parent: 900000000, len: 40000000
regs: 2b000000, 01000000
config: 940000000, 10000000
fdt_device_get_interrupt("pcie@2B000000", 0)
stgArfun: 0xc0
stgAwfun: 0xc4
stgRpNep: 0x130
stgLnksta: 0x1b8
clock[JH7110_NOC_BUS_CLK_STG_AXI]: 1
clock[JH7110_PCIE0_CLK_TL]: 0
clock[JH7110_PCIE0_CLK_AXI_MST0]: 0
clock[JH7110_PCIE0_CLK_APB]: 0
reset[RSTN_U0_PLDA_PCIE_AXI_MST0]: 0
reset[RSTN_U0_PLDA_PCIE_AXI_SLV0]: 0
reset[RSTN_U0_PLDA_PCIE_AXI_SLV]: 0
reset[RSTN_U0_PLDA_PCIE_BRG]: 0
reset[RSTN_U0_PLDA_PCIE_CORE]: 0
reset[RSTN_U0_PLDA_PCIE_APB]: 0
init clocks and resets
clk-gate: readl(ffffffc000fde180) -> 0x80000000
clk-gate: writel(0x80000000, ffffffc000fde180) ->
clk-gate: readl(ffffffc000fee028) -> 0x0
clk-gate: writel(0x80000000, ffffffc000fee028) ->
clk-gate: readl(ffffffc000fee020) -> 0x0
clk-gate: writel(0x80000000, ffffffc000fee020) ->
clk-gate: readl(ffffffc000fee024) -> 0x0
clk-gate: writel(0x80000000, ffffffc000fee024) ->
reset: readl(ffffffc0069a1074) -> 0x7ffffe
reset: writel(0x7ff7fe, ffffffc0069a1074)
reset: readl(ffffffc0069a1074) -> 0x7ff7fe
reset: writel(0x7fe7fe, ffffffc0069a1074)
reset: readl(ffffffc0069a1074) -> 0x7fe7fe
reset: writel(0x7fc7fe, ffffffc0069a1074)
reset: readl(ffffffc0069a1074) -> 0x7fc7fe
reset: writel(0x7f87fe, ffffffc0069a1074)
reset: readl(ffffffc0069a1074) -> 0x7f87fe
reset: writel(0x7f07fe, ffffffc0069a1074)
reset: readl(ffffffc0069a1074) -> 0x7f07fe
reset: writel(0x7e07fe, ffffffc0069a1074)
pinctrl: readl(ffffffc0069e1058) -> 0x700
pinctrl: writel(0x700, ffffffc0069e1058) ->
pinctrl: readl(ffffffc0069e1018) -> 0x0
pinctrl: writel(0x0, ffffffc0069e1018) ->
ATR entry: 0x0940000000 -> 0x0000000000 [0x0010000000] (param: 0x000001)
ATR entry: 0x0030000000 -> 0x0030000000 [0x0008000000] (param: 0x000000)
ATR entry: 0x0900000000 -> 0x0900000000 [0x0040000000] (param: 0x000000)
pinctrl: readl(ffffffc0069e1058) -> 0x700
pinctrl: writel(0x10700, ffffffc0069e1058) ->
pinctrl: readl(ffffffc0069e1018) -> 0x0
pinctrl: writel(0x0, ffffffc0069e1018) ->
MsiInterruptCtrlPlda::Init()
irq: 56
fMsiPhysAddr: 0x190
allocate_io_interrupt_vectors: allocated 32 vectors starting from 137
fMsiStartIrq: 137
-PciControllerPlda::InitDriver()
pci_init_deferred()
count: 0
+PciControllerPlda::InitDriver()
bus-range: 0 - 255
interrupt-map:
bus: 0, dev: 0, fn: 0, childIrq: 1, parentIrq: (5, 1)
bus: 0, dev: 0, fn: 0, childIrq: 2, parentIrq: (5, 2)
bus: 0, dev: 0, fn: 0, childIrq: 3, parentIrq: (5, 3)
bus: 0, dev: 0, fn: 0, childIrq: 4, parentIrq: (5, 4)
ranges:
MMIO32 (0x82000000): child: 38000000, parent: 38000000, len: 8000000
MMIO64 (0xc3000000): child: 980000000, parent: 980000000, len: 40000000
regs: 2c000000, 01000000
config: 9c0000000, 10000000
fdt_device_get_interrupt("pcie@2C000000", 0)
stgArfun: 0x270
stgAwfun: 0x274
stgRpNep: 0x2e0
stgLnksta: 0x368
clock[JH7110_NOC_BUS_CLK_STG_AXI]: 1
clock[JH7110_PCIE1_CLK_TL]: 0
clock[JH7110_PCIE1_CLK_AXI_MST0]: 0
clock[JH7110_PCIE1_CLK_APB]: 0
reset[RSTN_U1_PLDA_PCIE_AXI_MST0]: 0
reset[RSTN_U1_PLDA_PCIE_AXI_SLV0]: 0
reset[RSTN_U1_PLDA_PCIE_AXI_SLV]: 0
reset[RSTN_U1_PLDA_PCIE_BRG]: 0
reset[RSTN_U1_PLDA_PCIE_CORE]: 0
reset[RSTN_U1_PLDA_PCIE_APB]: 0
init clocks and resets
clk-gate: readl(ffffffc000fde180) -> 0x80000000
clk-gate: writel(0x80000000, ffffffc000fde180) ->
clk-gate: readl(ffffffc000fee034) -> 0x0
clk-gate: writel(0x80000000, ffffffc000fee034) ->
clk-gate: readl(ffffffc000fee02c) -> 0x0
clk-gate: writel(0x80000000, ffffffc000fee02c) ->
clk-gate: readl(ffffffc000fee030) -> 0x0
clk-gate: writel(0x80000000, ffffffc000fee030) ->
reset: readl(ffffffc0069a1074) -> 0x7e07fe
reset: writel(0x7c07fe, ffffffc0069a1074)
reset: readl(ffffffc0069a1074) -> 0x7c07fe
reset: writel(0x7807fe, ffffffc0069a1074)
reset: readl(ffffffc0069a1074) -> 0x7807fe
reset: writel(0x7007fe, ffffffc0069a1074)
reset: readl(ffffffc0069a1074) -> 0x7007fe
reset: writel(0x6007fe, ffffffc0069a1074)
reset: readl(ffffffc0069a1074) -> 0x6007fe
reset: writel(0x4007fe, ffffffc0069a1074)
reset: readl(ffffffc0069a1074) -> 0x4007fe
reset: writel(0x7fe, ffffffc0069a1074)
pinctrl: readl(ffffffc0069e105c) -> 0x0
pinctrl: writel(0x0, ffffffc0069e105c) ->
pinctrl: readl(ffffffc0069e101c) -> 0x0
pinctrl: writel(0x0, ffffffc0069e101c) ->
ATR entry: 0x09c0000000 -> 0x0000000000 [0x0010000000] (param: 0x000001)
ATR entry: 0x0038000000 -> 0x0038000000 [0x0008000000] (param: 0x000000)
ATR entry: 0x0980000000 -> 0x0980000000 [0x0040000000] (param: 0x000000)
pinctrl: readl(ffffffc0069e105c) -> 0x0
pinctrl: writel(0x1, ffffffc0069e105c) ->
pinctrl: readl(ffffffc0069e101c) -> 0x0
pinctrl: writel(0x0, ffffffc0069e101c) ->
MsiInterruptCtrlPlda::Init()
irq: 57
fMsiPhysAddr: 0x190
allocate_io_interrupt_vectors: allocated 32 vectors starting from 169
fMsiStartIrq: 169
-PciControllerPlda::InitDriver()
pci_init_deferred()
count: 1
PCI: EnumerateBus: domain 0, bus 0
PCI: found PCI-PCI bridge: domain 0, bus 0, dev 0, func 0
PCI: original settings: pcicmd 0000, primary-bus 0, secondary-bus 0, subordinate-bus 0
PCI: disabled settings: pcicmd 0000, primary-bus 0, secondary-bus 0, subordinate-bus 0
PCI: configuring PCI-PCI bridge: domain 0, bus 0, dev 0, func 0
PCI: probing settings: pcicmd 0006, primary-bus 0, secondary-bus 1, subordinate-bus 255
PCI: EnumerateBus: domain 0, bus 1
PCI: EnumerateBus done: domain 0, bus 1, last used bus number 1
PCI: configured settings: pcicmd 0006, primary-bus 0, secondary-bus 1, subordinate-bus 1
PCI: EnumerateBus done: domain 0, bus 0, last used bus number 1
PCI: EnumerateBus: domain 1, bus 0
PCI: found PCI-PCI bridge: domain 1, bus 0, dev 0, func 0
PCI: original settings: pcicmd 0000, primary-bus 0, secondary-bus 0, subordinate-bus 0
PCI: disabled settings: pcicmd 0000, primary-bus 0, secondary-bus 0, subordinate-bus 0
PCI: configuring PCI-PCI bridge: domain 1, bus 0, dev 0, func 0
PCI: probing settings: pcicmd 0006, primary-bus 0, secondary-bus 1, subordinate-bus 255
PCI: EnumerateBus: domain 1, bus 1
PCI: EnumerateBus done: domain 1, bus 1, last used bus number 1
PCI: configured settings: pcicmd 0006, primary-bus 0, secondary-bus 1, subordinate-bus 1
PCI: EnumerateBus done: domain 1, bus 0, last used bus number 1
PCI: FixupDevices domain 0, bus 0
PCI: FixupDevices: checking bus 1 behind 1556:1111
PCI: FixupDevices domain 0, bus 1
PCI: FixupDevices domain 1, bus 0
PCI: FixupDevices: checking bus 1 behind 1556:1111
PCI: FixupDevices domain 1, bus 1
PCI: DiscoverBus, domain 0, bus 0
PCI: DiscoverDevice, domain 0, bus 0, dev 0, func 0
PCI: CreateDevice, domain 0, bus 0, dev 0, func 0:
PCI::CreateVirtualBus: domain 0, bus 0 => virtualBus 0
PCI: CreateDevice, vendor 0x1556, device 0x1111, class_base 0x06, class_sub 0x04
PCI: DiscoverBus, domain 0, bus 1
PCI: DiscoverDevice, domain 0, bus 1, dev 0, func 0
PCI: CreateDevice, domain 0, bus 1, dev 0, func 0:
PCI::CreateVirtualBus: domain 0, bus 1 => virtualBus 1
PCI: CreateDevice, vendor 0x1106, device 0x3483, class_base 0x0c, class_sub 0x03
PCI: DiscoverBus, domain 1, bus 0
PCI: DiscoverDevice, domain 1, bus 0, dev 0, func 0
PCI: CreateDevice, domain 1, bus 0, dev 0, func 0:
PCI::CreateVirtualBus: domain 1, bus 0 => virtualBus 2
PCI: CreateDevice, vendor 0x1556, device 0x1111, class_base 0x06, class_sub 0x04
PCI: DiscoverBus, domain 1, bus 1
PCI: DiscoverDevice, domain 1, bus 1, dev 0, func 0
PCI: CreateDevice, domain 1, bus 1, dev 0, func 0:
PCI::CreateVirtualBus: domain 1, bus 1 => virtualBus 3
PCI: CreateDevice, vendor 0x1987, device 0x5013, class_base 0x01, class_sub 0x08
PCI: dom 0, bus 0, dev 0, func 0, changed PCI bridge control from 0x0000 to 0x0003
PCI: dom 1, bus 0, dev 0, func 0, changed PCI bridge control from 0x0000 to 0x0003
PCI::CreateVirtualBus: domain 0, bus 0 already in map => virtualBus 0
PCI:FindHTCapability ERROR 0:0:0 capability 0xa800 not supported
PCI::CreateVirtualBus: domain 0, bus 1 already in map => virtualBus 1
PCI:FindHTCapability ERROR 1:0:0 capability 0xa800 not supported
PCI::CreateVirtualBus: domain 1, bus 0 already in map => virtualBus 2
PCI:FindHTCapability ERROR 0:0:0 capability 0xa800 not supported
PCI::CreateVirtualBus: domain 1, bus 1 already in map => virtualBus 3
PCI:FindHTCapability ERROR 1:0:0 capability 0xa800 not supported
PCI: [dom 0, bus 0] bus 0, device 0, function 0: vendor 1556, device 1111, revision 02
PCI: class_base 06, class_function 04, class_api 00
PCI: line_size 00, latency 00, header_type 01, BIST 00
PCI: subsystem_id 0000, subsystem_vendor_id 0080
PCI: primary_bus 00, secondary_bus 01, subordinate_bus 01, secondary_latency 00
PCI: I/O window 0000-0fff
PCI: memory window 00000000-000fffff
PCI: prefetchable memory window 0000000000000000-00000000000fffff
PCI: bridge_control 0003, secondary_status 0000
PCI: interrupt_line 00, interrupt_pin 01
PCI: ROM base host 00000000, pci 00000000, size ??
PCI: base reg 0: host 00000000, pci 00000000, size 00004000, flags 0c
PCI: base reg 1: host 00000000, pci 00000000, size 00000000, flags 00
PCI: Capabilities: PCIe, MSI, PM
PCI: Extended capabilities: Vendor Unique, Advanced Error Reporting
PCI: [dom 0, bus 1] bus 1, device 0, function 0: vendor 1106, device 3483, revision 01
PCI: class_base 0c, class_function 03, class_api 30
PCI: line_size 00, latency 00, header_type 00, BIST 00
PCI: ROM base host 00000000, pci 00000000, size 00000000
PCI: cardbus_CIS 00000000, subsystem_id 3483, subsystem_vendor_id 1106
PCI: interrupt_line 00, interrupt_pin 01, min_grant 00, max_latency 00
PCI: base reg 0: host 0000000000000000, pci 0000000000000000, size 00001000, flags 04 00
PCI: base reg 2: host 00000000, pci 00000000, size 00000000, flags 00
PCI: base reg 3: host 00000000, pci 00000000, size 00000000, flags 00
PCI: base reg 4: host 00000000, pci 00000000, size 00000000, flags 00
PCI: base reg 5: host 00000000, pci 00000000, size 00000000, flags 00
PCI: Capabilities: PM, MSI, PCIe
PCI: Extended capabilities: Advanced Error Reporting
PCI: [dom 1, bus 0] bus 2, device 0, function 0: vendor 1556, device 1111, revision 02
PCI: class_base 06, class_function 04, class_api 00
PCI: line_size 00, latency 00, header_type 01, BIST 00
PCI: subsystem_id 0000, subsystem_vendor_id 0080
PCI: primary_bus 00, secondary_bus 01, subordinate_bus 01, secondary_latency 00
PCI: I/O window 0000-0fff
PCI: memory window 00000000-000fffff
PCI: prefetchable memory window 0000000000000000-00000000000fffff
PCI: bridge_control 0003, secondary_status 0000
PCI: interrupt_line 00, interrupt_pin 01
PCI: ROM base host 00000000, pci 00000000, size ??
PCI: base reg 0: host 00000000, pci 00000000, size 00004000, flags 0c
PCI: base reg 1: host 00000000, pci 00000000, size 00000000, flags 00
PCI: Capabilities: PCIe, MSI, PM
PCI: Extended capabilities: Vendor Unique, Advanced Error Reporting
PCI: [dom 1, bus 1] bus 3, device 0, function 0: vendor 1987, device 5013, revision 01
PCI: class_base 01, class_function 08, class_api 02
PCI: line_size 00, latency 00, header_type 00, BIST 00
PCI: ROM base host 00000000, pci 00000000, size 00000000
PCI: cardbus_CIS 00000000, subsystem_id 5013, subsystem_vendor_id 1987
PCI: interrupt_line 00, interrupt_pin 01, min_grant 00, max_latency 00
PCI: base reg 0: host 0000000000000000, pci 0000000000000000, size 00004000, flags 04 00
PCI: base reg 2: host 00000000, pci 00000000, size 00000000, flags 00
PCI: base reg 3: host 00000000, pci 00000000, size 00000000, flags 00
PCI: base reg 4: host 00000000, pci 00000000, size 00000000, flags 00
PCI: base reg 5: host 00000000, pci 00000000, size 00000000, flags 00
PCI: Capabilities: PCIe, MSI-X, MSI, PM
PCI: Extended capabilities: Latency Tolerance Reporting, L1 Power Management Substates, Advanced Error Reporting, Secondary PCIe
slab memory manager: created area 0xffffffc001801000 (1063)
PANIC: Unexpected exception occurred in kernel mode!
Welcome to Kernel Debugging Land...
Thread 17 "main2" running on CPU 2
Stack:
FP: 0xffffffc00687fc10
FP: 0xffffffc00687fc30, PC: 0xffffffc002155106 <kernel_riscv64> arch_debug_call_with_fault_handler + 32
FP: 0xffffffc00687fc80, PC: 0xffffffc0020d5e20 <kernel_riscv64> debug_call_with_fault_handler.localalias + 128
FP: 0xffffffc00687fd10, PC: 0xffffffc0020d71a0 <kernel_riscv64> _ZL20kernel_debugger_loopPKcS0_Pvi + 320
FP: 0xffffffc00687fd80, PC: 0xffffffc0020d7546 <kernel_riscv64> _ZL24kernel_debugger_internalPKcS0_Pvi + 284
FP: 0xffffffc00687fdc0, PC: 0xffffffc0020d77d8 <kernel_riscv64> panic + 86
FP: 0xffffffc00687fef0, PC: 0xffffffc0021561e6 <kernel_riscv64> STrap + 594
FP: 0xffffffc006880010, PC: 0xffffffc002153f60 <kernel_riscv64> SVec + 96
STrap(exception loadAccessFault)
sstatus: (ie: {}, pie: {s}, spp: s, fs: dirty, xs: off, sum: 0, mxr: 0, uxl: 2, sd: 1)
stval: 0xffffffc006837000
ra: 0xffffffc00255e3e0 t6: 0x0000000000000020 sp: 0xffffffc006880010 gp: 0x0000000000000000
tp: 0xffffffc0072cb580 t0: 0xffffffc00218e540 t1: 0xffffffc00207d9dc t2: 0x0000000000000000
t5: 0x0000000000000000 s1: 0xffffffc001006000 a0: 0x0000000000000428 a1: 0x0000000000010000
a2: 0x0000000000000090 a3: 0xffffffffffffffff a4: 0x0000000000000001 a5: 0xffffffc006837000
a6: 0xffffffc00215ae8c a7: 0xffffffc002264710 s2: 0x0000000000051000 s3: 0xffffffc00720ed20
s4: 0xffffffc007756160 s5: 0xffffffc0024b36b0 s6: 0xffffffc0077b88f0 s7: 0xffffffc0068801d0
s8: 0x0000000000000000 s9: 0x0000000000000018 s10: 0xffffffc002708156 s11: 0xffffffc006880a18
t3: 0xffffffc0020a96d6 t4: 0x0000000000001000 fp: 0xffffffc0068800a0 epc: 0xffffffc00255e3f4
FP: 0xffffffc0068800a0, PC: 0xffffffc00255e3f4 <xhci> _ZN4XHCIC2EP8pci_infoP22pci_device_module_infoP10pci_deviceP5StackP11device_node.localalias + 340
FP: 0xffffffc0068800f0, PC: 0xffffffc00255eaf8 <xhci> _ZL8init_busP11device_nodePPv + 134
FP: 0xffffffc006880120, PC: 0xffffffc0020e81e2 <kernel_riscv64> _ZN11device_node10InitDriverEv.localalias + 108
FP: 0xffffffc006880160, PC: 0xffffffc0020e9a30 <kernel_riscv64> _ZN11device_node8RegisterEPS_.localalias + 42
FP: 0xffffffc0068801b0, PC: 0xffffffc0020e9ba4 <kernel_riscv64> _ZL13register_nodeP11device_nodePKcPK11device_attrPK11io_resourcePS0_ + 160
FP: 0xffffffc006880250, PC: 0xffffffc00255cc78 <xhci> _ZL22register_child_devicesPv + 164
FP: 0xffffffc006880290, PC: 0xffffffc0020e9a5e <kernel_riscv64> _ZN11device_node8RegisterEPS_.localalias + 88
FP: 0xffffffc0068802e0, PC: 0xffffffc0020e9ba4 <kernel_riscv64> _ZL13register_nodeP11device_nodePKcPK11device_attrPK11io_resourcePS0_ + 160
FP: 0xffffffc006880330, PC: 0xffffffc00255ca20 <xhci> _ZL15register_deviceP11device_node + 100
FP: 0xffffffc0068803b0, PC: 0xffffffc0020e910c <kernel_riscv64> _ZN11device_node16_RegisterDynamicEPS_.localalias + 220
FP: 0xffffffc0068803f0, PC: 0xffffffc0020e9a9c <kernel_riscv64> _ZN11device_node8RegisterEPS_.localalias + 150
FP: 0xffffffc006880440, PC: 0xffffffc0020e9ba4 <kernel_riscv64> _ZL13register_nodeP11device_nodePKcPK11device_attrPK11io_resourcePS0_ + 160
FP: 0xffffffc006880690, PC: 0xffffffc0024afc42 <pci> _ZL31pci_root_register_child_devicesPv + 454
FP: 0xffffffc0068806d0, PC: 0xffffffc0020e9a5e <kernel_riscv64> _ZN11device_node8RegisterEPS_.localalias + 88
FP: 0xffffffc006880720, PC: 0xffffffc0020e9ba4 <kernel_riscv64> _ZL13register_nodeP11device_nodePKcPK11device_attrPK11io_resourcePS0_ + 160
FP: 0xffffffc006880790, PC: 0xffffffc0024afa44 <pci> _ZL24pci_root_register_deviceP11device_node + 142
FP: 0xffffffc0068807f0, PC: 0xffffffc0020e8692 <kernel_riscv64> _ZN11device_node14_RegisterFixedERj.localalias + 96
FP: 0xffffffc006880830, PC: 0xffffffc0020e9a50 <kernel_riscv64> _ZN11device_node8RegisterEPS_.localalias + 74
FP: 0xffffffc006880880, PC: 0xffffffc0020e9ba4 <kernel_riscv64> _ZL13register_nodeP11device_nodePKcPK11device_attrPK11io_resourcePS0_ + 160
FP: 0xffffffc0068808f0, PC: 0xffffffc0024b6960 <plda> _ZN17PciControllerPlda14RegisterDeviceEP11device_node + 136
FP: 0xffffffc006880970, PC: 0xffffffc0020e910c <kernel_riscv64> _ZN11device_node16_RegisterDynamicEPS_.localalias + 220
FP: 0xffffffc0068809b0, PC: 0xffffffc0020e9a9c <kernel_riscv64> _ZN11device_node8RegisterEPS_.localalias + 150
FP: 0xffffffc006880a00, PC: 0xffffffc0020e9ba4 <kernel_riscv64> _ZL13register_nodeP11device_nodePKcPK11device_attrPK11io_resourcePS0_ + 160
FP: 0xffffffc006880ad0, PC: 0xffffffc0023aa43e <fdt> _ZL17fdt_register_nodeP7fdt_busiP11device_nodeRS2_.isra.0 + 632
FP: 0xffffffc006880b10, PC: 0xffffffc0023aa6de <fdt> _ZL12fdt_traverseP7fdt_busRiS1_P11device_node + 42
FP: 0xffffffc006880b50, PC: 0xffffffc0023aa716 <fdt> _ZL12fdt_traverseP7fdt_busRiS1_P11device_node + 98
FP: 0xffffffc006880b90, PC: 0xffffffc0023aa716 <fdt> _ZL12fdt_traverseP7fdt_busRiS1_P11device_node + 98
FP: 0xffffffc006880bc0, PC: 0xffffffc0023aa778 <fdt> _ZL30fdt_bus_register_child_devicesPv + 76
FP: 0xffffffc006880c00, PC: 0xffffffc0020e9a5e <kernel_riscv64> _ZN11device_node8RegisterEPS_.localalias + 88
FP: 0xffffffc006880c50, PC: 0xffffffc0020e9ba4 <kernel_riscv64> _ZL13register_nodeP11device_nodePKcPK11device_attrPK11io_resourcePS0_ + 160
FP: 0xffffffc006880cc0, PC: 0xffffffc0023a90ea <fdt> _ZL23fdt_bus_register_deviceP11device_node + 142
FP: 0xffffffc006880d10, PC: 0xffffffc0020e8f2c <kernel_riscv64> _ZN11device_node13_RegisterPathEPKc.localalias + 78
FP: 0xffffffc006880d90, PC: 0xffffffc0020e9146 <kernel_riscv64> _ZN11device_node16_RegisterDynamicEPS_.localalias + 278
FP: 0xffffffc006880dd0, PC: 0xffffffc0020e9a9c <kernel_riscv64> _ZN11device_node8RegisterEPS_.localalias + 150
FP: 0xffffffc006880e20, PC: 0xffffffc0020e9ba4 <kernel_riscv64> _ZL13register_nodeP11device_nodePKcPK11device_attrPK11io_resourcePS0_ + 160
FP: 0xffffffc006880f60, PC: 0xffffffc0020e9cfa <kernel_riscv64> _ZL14init_node_treev + 184
FP: 0xffffffc006880f70, PC: 0xffffffc0020ea4c0 <kernel_riscv64> device_manager_init + 336
FP: 0xffffffc006880fc0, PC: 0xffffffc002098530 <kernel_riscv64> _ZL5main2Pv + 162
FP: 0xffffffc006880fe0, PC: 0xffffffc0020ba188 <kernel_riscv64> _ZL19common_thread_entryPv + 52
FP: 0x0, PC: 0xffffffc002153ed8 <kernel_riscv64> arch_thread_entry + 0
17 Likes
My VF2 just arrive. I’am tested it. Work on Debian. Now I wait for X512 works with a little stable version of Haiku for RiscV.
Cheers!
1 Like
Congrats on getting Haiku booting on the VF2 so quickly X512! Super impressive work yet again.
I’ve ordered one now, overcome with the sheer novelty value of being able to run Haiku on a new and exciting arch. Hopefully you’ll be able to get USB working before mine arrives? 
This has made me wonder. How is it that you’ve been able to get Haiku booting to the desktop and mostly usable on at least two RV boards now but we still don’t have a comparable status ARM port of Haiku when many more devs have had access to ARM boards for much longer than we’ve had RV SBCs?
ARM has never been a good target. ARM has so many different architectures and ways to boot. Each of them being more like its own platform and needing different drivers. It has been a moving target all this time. IIRC Haiku almost booted on gumstix arm boards, but who even remembers them now?
It is starting to become simpler with UEFI, ACPI and devicetrees, ARM chips still need a lot of different drivers. The Risc-V port also made haiku a lot more portable which also helps ARM and other targets.
And the most important part: there needs to be a person willing to spend time and energy on it, it is a hard task and it is hard to stay motivated. So keep motivating and encouraging people…
15 Likes
63 Likes
That is super hot! Would love to try this soon. <3
Amazing! Less than three hours after I posted you have USB working! Is that USB 2.0 and 3.0?
I presume the visionfive 2 HDMI doesn’t support audio yet does it? I’ve got some dirt cheap USB C headphone adapters (“sounds cards”) I’ll have to see if they work with haiku x86 then maybe I can use it on RV for audio? I presume the onboard audio isn’t supported yet?
It is XHCI (USB 3).
It will probably work in the same way as in x86 (with some glitches).
There are an audio jack on the left side. It is not supported yet by Haiku but seems not complicated to support.
10 Likes
So how is performance on this board? is it worth buying?, great work BTW, the speed at which you make progress is impressive, it makes us happy to see it every time.
5 Likes
X512 may correct me if he knows better but the phoronix benchmarks I saw put it in the same ballpark as a RPi 3 in terms of its CPU. This will partly be because all compilers, libraries and apps are optimised for x86 and/or ARM but not RISCV yet.
EDIT
I’m not sure phoronix have benchmarked the visionfive 2 yet so maybe I was thinking of tests they did on the Unmatched. I don’t think there’s a world of difference between the two tho so my comparison could still be good enough. I’m not expecting it to be as fast as my RPi 4 but I’m encouraged by the fact it has an open source mesa GPU driver in the works.
Optimization to riscv maybe be a 10-15% cpu speed. RPi4 prize is now very unsatisfacted, because ARM on RPi4 is fast. Vision Five have a other issures, like m.2 port or UEFI in Uboot. The Power o RiscV is open architeture and software drivers. Maybe a SWOT analise (+ and -) talk you more.
There might also be a lack of developer interest in an ARM port due to ARM being a closed ISA.
The Core of ARM is under licence and it’s cost (high price), many of developer choose a ARM becase is in new technlogy and monetary gain. Majority of Engeeners don’t like RISCV, open project is excelent to open source, not for monetization. An idea of SBC is not a speed.
Many of years be a intel 8051, now when RPi look a light of sun, the era of old intel pass.
1 Like
tqh summed up the problem very well. It is not so much lack of interest, but lack of time and ever changing hardware. I have over the years bought several ARM devices, and each of them became obsolete and possibly broken before I could even get started on porting Haiku to it. I still own some of them, and maybe I’ll get back to Haiku hacking on at least one (the other is way too old and it would not make sense anymore to get Haiku running there, and the architecture is very strange, 2 CPU cores of which only one has an MMU…)
There is no problem at all with it being a “closed” ISA (what does that even mean? That issue has been solved since at least the 6502 cloning the ISA of the Motorola 6800 but swapping the CPU pins around so it wouldn’t be fully compatible, or the z80 being a clone of the 8080 but renaming the mnemonics in the assembler so people would notice, but lawyers wouldn’t).
There were problems with each machine using an ARM CPU being essentially a completely different architecture, with a different UART to send debug to, a different way to program the framebuffer, and so on. When we started, even the MMU wasn’t standard and was different between various ARM generations.
Recently this is solved by having UEFI for all machines, meaning we can get at least the bootloader running on any machine without any new code. This benefits both RISC-V and ARM, since they have both standardized on UEFI, and as a result, the ARM port has started to make some progress again.
So, TL;DR: it is not a problem of closed ISA, but of lack of architecture standardization for anything but the CPU itself.
8 Likes
Not visionfive 2 but Haiku generally not supports audio over hdmi.
Well, that all depends on the drivers. On modern x86 PCs with Intel graphics, it is not done yet because it requires collaboration between the graphics driver and the sound driver, both of which are rather complicated things designed by Intel. But on other chipset designs, it may be a lot easier.
This probably would be good to post as an official haiku news post. Do not ask me how though…
4 Likes